Alphawave Semi (LSE: AWE; formerly Alphawave IP) says it has brought up its ZeusCORE Extra-Long-Reach (XLR) 1- to 112-Gbps NRZ/PAM4 SerDes IP via TSMC’s 3-nm process. The company revealed plans to conduct a live demonstration of the silicon platform with 112G Ethernet and PCIe 6.0 IP on TSMC 3-nm process this week at the TSMC North America Symposium in Santa Clara, CA.
The company asserts that ZeusCORE XLR Multi-Standard-Serdes (MSS) IP and its 3-nm-enabled performance will help enable the development of high-performance AI systems. Alphawave Semi also states that the IP supports all “leading edge” NRZ and PAM4 data center standards from 1 to 112 Gbps as well as such protocols as PCIe Gen1 to Gen6 and 1G/10G/25G/50G/100-Gbps Ethernet.
The IP also can be paired with Alphawave Semi's chiplet-enabled custom silicon platform, which includes IO, memory, and compute chiplets. Alphawave Semi’s application-optimized IP subsystems and 2.5D/3D packaging expertise also can be combined to integrate such interfaces as Compute Express Link (CXL), Universal Chiplet Interconnect Express (UCIe), High Bandwidth Memory (HBMx), and Low-Power Double Data Rate DRAM (LP/DDRx/) onto custom chips and chiplets.
“We are thrilled to be one of the first companies to successfully demonstrate our highest performance silicon platform with our XLR 112G Ethernet and PCIE6.0 SerDes IP on TSMC’s most advanced 3-nm technology,” said Tony Pialis, CEO and co-founder of Alphawave Semi. “This represents a significant step forward in our execution of Alphawave Semi’s strategy to be a vertically integrated semiconductor leader in high-speed connectivity. Thanks to our rapidly growing partnership with TSMC through the Open Innovation Platform (OIP), we continue to deliver innovative, high-performance custom silicon and IP solutions to our customers in data center, compute, networking, AI, 5G, autonomous vehicles, and storage applications.”
“Alphawave Semi continues to see growing demand from our hyperscaler customers for purpose-built silicon with very high-speed connectivity interfaces, fueled by an exponential increase in processing of AI-generated data,” added Mohit Gupta, senior vice president and general manager, custom silicon and IP, at Alphawave Semi. “We're engaging our leading customers on chiplet-enabled 3-nm custom silicon platforms which include IO, memory, and compute chiplets. Our Virtual Channel Aggregator (VCA) partnership with TSMC has provided invaluable support, and we look forward to accelerating our customers' high-performance designs on TSMC's 3-nm process.”
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Stephen Hardy | Editorial Director and Associate Publisher, Lightwave
Stephen Hardy is editorial director and associate publisher of Lightwave and Broadband Technology Report, part of the Lighting & Technology Group at Endeavor Business Media. Stephen is responsible for establishing and executing editorial strategy across the both brands’ websites, email newsletters, events, and other information products. He has covered the fiber-optics space for more than 20 years, and communications and technology for more than 35 years. During his tenure, Lightwave has received awards from Folio: and the American Society of Business Press Editors (ASBPE) for editorial excellence. Prior to joining Lightwave in 1997, Stephen worked for Telecommunications magazine and the Journal of Electronic Defense.
Stephen has moderated panels at numerous events, including the Optica Executive Forum, ECOC, and SCTE Cable-Tec Expo. He also is program director for the Lightwave Innovation Reviews and the Diamond Technology Reviews.
He has written numerous articles in all aspects of optical communications and fiber-optic networks, including fiber to the home (FTTH), PON, optical components, DWDM, fiber cables, packet optical transport, optical transceivers, lasers, fiber optic testing, and more.
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