Infineon unveils high-integration, multi-channel Tethys SONET/SDH framer chips

7 July 2003 Munich, Germany Lightwave -- Infineon Technologies AG today announced the addition of what it claims are the most highly integrated multi-rate, multi-channel, high-data-rate SONET/SDH framer chips. The new Tethys SONET/SDH Multi-Rate Framer family of ICs provides--in one chip--functions that are critical for next-generation optical networking equipment in such applications as add/drop multiplexers (ADMs) and digital cross-connect switches.

The new ICs allow manufacturers to increase line card port count and capacity while decreasing per-port cost and power, claims the company. They also allow a single line card design to be configured for multiple data rates by simply changing the optical modules attached to it.

The single-chip Tethys devices integrate functions previously requiring up to five separate components, including aggregation of up to 16 channels of traffic, serializing/deserializing, pointer processing, clock and data recovery, and transport overhead (TOH) and path overhead (POH) processing. This is the highest degree of integration of any SONET/SDH framer chip in its class, say Infineon representatives, effectively creating the first high-density "line card on a chip." Use of the Tethys framers can result in significant savings for manufacturers of line cards for trunk, tributary, and service applications in terms of power consumption, board design complexity and space, software development, and overall system cost.

The first two members of the new framer family, the Tethys 448 and Tethys 4192, support high-density aggregate throughputs while meeting the most stringent SONET/SDH jitter requirements. The Tethys 448 fully supports 16 channels of OC-3/STM-1, 16 channels of OC-12/STM-4, or 16 channels of OC-48/STM-16, which can be mixed in any required combination. In addition to the Tethys 448 capabilities, the Tethys 4192 adds support for four channels of OC-192/STM-64.

The Tethys framers allow every port to be independently set for a different data rate, permitting "any port, any rate" configuration, and provide a direct interface to optical modules. This enables equipment to be programmed in the field by simply changing the optical modules, which enables service providers to purchase one card for use in multiple applications, reducing maintenance costs, in-service upgrades, and inventory.

"Service providers are constantly looking for ways to reduce the cost of new network builds," explains Allan Armstrong, program director at telecommunications industry analyst firm RHK. "To reduce R&D and production costs, system vendors are now replacing legacy framer ASICs with newer standard products. Unified framer solutions that support a variety of data rates with a common hardware and software architecture allow system vendors to leverage their engineering efforts, greatly cutting costs for new platforms," he adds. "Improvements in integration also help system vendors make denser line cards, which makes their products more competitive in both edge and core applications."

Tethys multi-rate framer features:
The Tethys Multi-Rate SONET/DSH Framer chips are highly integrated devices that implement full-duplex SONET/SDH processing at OC-3/STM-1, OC-12/STM-4, OC-48/STM-16 or OC-192/STM-64 data rates. Included in the functions they perform are section, line, and path overhead processing; framing; scrambling/descrambling; alarm signal insertion/detection; bit-interleaved parity (B1/B2/B3) processing; and pointer processing. In addition, they feature a unique hardware Forced Input Path (FIP) capability that allows an entire path to be overwritten directly in alarm conditions, eliminating the need to involve the CPU and switch matrix.

Alarm drop interfaces detect such conditions as loss of signal (LOS) and loss of frame (LOF), and enable the FIP function together with the POH handling.

Unlike other framer chips, which typically offer access to TOH only, the Tethys architecture allows both TOH and POH bytes to be extracted from and re-inserted into the receive and transmit paths, say company representatives, making all overhead bytes available for additional processing.

On-chip serializer/deserializer (SERDES), clock and data recovery (CDR), and clock multiplier unit (CMU) functions support 2.5-Gbit/sec, 622-Mbit/sec and 155-Mbit/sec multi-rate I/Os. Based on three previous generations of silicon, the Tethys framers support 32 CDRs on a single chip while still meeting the strictest SONET/SDH jitter requirements, including tolerance, transfer, and generation.

The line-side interfaces for the Tethys 448 framer are programmable serial ports. The Tethys 4192 chip has the additional interfaces, SFI-4.1 and SFI-4.2, required for the OC-192/STM-64 mode. The system-side interface for both devices supports TFI-5. The SFI-4.1, SFI-4.2 and TFI-5 interfaces are OIF-compliant. The selection and configuration of the line- and system-side interfaces are completely independent.

The Tethys 448 and Tethys 4192 framer chips will be offered in 1400-contact ball grid array (BGA) packages. Samples of both chips will be available in the third quarter of 2003, with volume production planned for later in the year. The Tethys 448, supporting up to 16 channels of OC-48 data, will be priced at $1,450 in sample quantities. The Tethys 4192, supporting up to four channels of OC-192 data, will be priced at $1,750 in sample quantities.