Fujitsu, Socionext develop 56-Gbps transceiver chip

Fujitsu Laboratories Ltd. and semiconductor supplier Socionext Inc. say they have developed a 56-Gbps transceiver circuit that consumes less power than any similar chip available. The companies believe the device will find use in servers, switches, and optical modules.

The collaborators say the circuit leverages a new timing error detection method that combines the decision feedback equalizer (DFE) with the clock and data recovery (CDR) circuit. The two functions traditionally account for about two-thirds of the transceiver circuit's total power consumption, the companies point out.

The new timing error detection method came about when, after analyzing waveforms after DFE calculation, Fujitsu Laboratories and Socionext discovered that they could detect whether the DFE's operational timing was early or late by comparing the results of the two DFE determination circuits in cases where three consecutive bits in the input signal were 100 or 011. The new timing detection method only detects the timing when three consecutive bits of the incoming signal are 100 or 011.

Use of this timing detection method enable the two companies to eliminate the previously required CDR incoming-signal timing-determination circuit, and lines, such as the clock line, which were required as the DFE and CDR operated with different timing. Thus, the companies could double performance to 56 Gbps with the same power consumption as slower-speed devices.

The two companies hope to release products that leverage the new technology by fiscal year 2018.

Details of this technology were announced at the recent IEEE International Solid-State Circuits Conference 2016 (ISSCC 2016).

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