Jitter control is critical to transponder performance

Jitter control in serializer/deserializer (SERDES) design is essential to the performance of optical transponder modules for communications applications. The three performance dimensions of jitter are generation, tolerance, and transfer. Each dimension must be carefully managed to produce compliant optical modules.

The interference signal applies a broad-frequency spectral disturbance that affects the position of the transition point in the signal of interest in the time domain. Although the interference signal is shown with a dominant sine wave in the time domain, in reality jitter is characterized by a Gaussian distribution convolved with a bound deterministic distribution in the frequency domain.

Jitter generation is a measure of the quantity of jitter on the output port of a network element. For G.707 SONET and related applications such as G.975 FEC and G.709 digital wrapper, the quantity of jitter is defined by the Bellcore document GR-253-CORE "Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria." The maximum jitter generation is 0.1UI in the frequency range from 50 KHz to 80 MHz with 20 dB per decade attenuation outside the passband.

Jitter generation is commonly measured on an oscilloscope using eye-mask techniques. However, this wideband measurement results in an inaccurate interpretation of the SONET jitter generation requirement. The IEEE 802.3ae 10-Gb/s Ethernet Task Force specifies output jitter in the form of a transmitter optical waveform (eye mask).

The clock generator within the transmitter is implemented in the clock multiplier unit (CMU) and contributes to the jitter generated by the SERDES. The CMU provides the 9.95328-GHz line rate from a 155.52- or 622.08-MHz external reference using a clock multiplier combined with a frequency divider in the feedback loop. It should be apparent that the accuracy of the line clock is a direct reflection of the external reference. To generate a line clock with a stability of 20 parts per million (ppm), a reference clock with 20-ppm stability is required. The jitter transfer from the reference clock to the internal VCO is controlled in part by the bandwidth of the loop filter.

The overall jitter generated by the SERDES is a complex function comprising many elements such as data-dependent jitter and intrinsic switching noise in the semiconductor. The CMU-associated jitter depends upon the frequency distribution of the reference clock and the transfer function of the clock generator. Any jitter below the cutoff frequency of the clock generator will add to the output jitter, in which case the high-frequency spectrum of the output jitter will be dominated by the jitter generated by the reference clock.

The SERDES receive-CDR is responsible for determining the ideal point in time to sample the incoming data stream. Typical CDR circuits employ a clock generator to track the region of stability on the eye mask. An ideal CDR has an infinite bandwidth that allows it to track the eye center in the presence of high- and low-frequency jitter. Practically, however, CDR circuits are designed to maintain stability during long runs of consecutive identical digits (CID) and minimum transition densities and are subsequently not agile enough to track very high-frequency deviations.

Design of the CDR is more complex than the CMU because of its dependence on the incoming data pattern. Whereas the CMU has a stable reference clock from which to derive the line rate, the CDR must be able to reliably produce a stable clock even during relatively long runs without an input transition. Poorly designed CDRs will wander during CID periods, causing the resulting output to drop or add bits. CDR designers must be aware of the maximum CID length for the intended SERDES application.

Essentially, the clock generator in the CDR must be highly agile to track the ideal sampling point in the presence of high jitter, and it must be extremely stable to avoid drifting during periods of CID. It is also worth noting that the jitter tolerance is not only a function of the input jitter but also a function of the jitter produced by the clock generator since this jitter will also interfere with the sampling point.

Jitter transfer must be controlled in all clock generator applications to reduce the amount of jitter passing through the clock generator from input to output. From a SONET perspective, jitter transfer is characterized in line timing applications when the recovered clock from the receiver is used as the clock reference for the line driver. It is defined as the ratio of received jitter to transmit jitter. Bellcore specifies a gain vs. frequency mask in GR-253-CORE. Maximum gain is 0.1 dB up to 120 KHz, then rolling off with a slope of 20 dB per decade. Jitter transfer is only applicable to SONET-based network elements and does not apply to 10 Gigabit Ethernet systems as they are only defined to operate in local timing mode.

Line timing is accomplished by substituting the reference clock with the recovered clock as the input to the transmit clock generator. Using a single, integrated SERDES component facilitates operation in-line timing applications by reducing interconnect associated with two-chip solutions.

Using the recovered clock generator directly for line timing applications generally provides unity gain (0 dB) across the bandwidth of the receiver. The CDR clock generator requires agility to track as much jitter as possible, but this agility causes wide-band jitter transfer to the output clock. Typically, this jitter is beyond the 120 KHz unity gain cut-off frequency. In other words, the unity gain bandwidth of the CDR and CMU is greater than the allowable unity gain bandwidth for line timing applications. To compensate for this and achieve the jitter transfer requirements of GR-253, the integrated, single-chip SERDES components provide a third clock generator that contains an interface for an external VCXO.

The clock generators contain second-order filtering to accept low frequencies and reject high frequencies. An under-damped frequency response results in gain peaking near the corner frequency of the filter. Peaking in a clock generator amplifies the jitter passed from input to output and is a significant contributor to excess jitter transfer. The external VCXO and an overdamped loop filter provides unity gain jitter transfer for low frequencies and significant jitter transfer attenuation at higher frequencies.

A single-chip SERDES device contains most of the elements required to provide compliant jitter transfer between the receiver and transmitter. The structure is essentially a two-stage clock generator, the first stage being the high bandwidth CDR for good jitter tolerance, and the second stage comprising the loop filter and VCXO with a very low loop bandwidth. The two stages are cascaded to produce a jitter transfer profile that meets the Bellcore jitter transfer specifications.

Tim Warland is an applications engineer at Quake Technologies, 80 Hines Rd., Kanata, ON K2K 2T8. He can be reached at [email protected].