Agere Systems (NYSE: AGR.A), a provider of communications components, has chosen Fujitsu's 256-megabit fast cycle random access memory (FCRAM) for use in its 10-gigabit-per-second (Gbit/s) wire-speed, carrier-class programmable PayloadPlus network processing architecture. The FCRAM technology will enable Agere's PayloadPlus family of network processing solutions to deliver the higher bandwidth, performance and speeds necessary for next-generation deep packet processing networks, at lower cost and using less space.
The PayloadPlus solution requires only FCRAM and a small amount of SRAM. Network FCRAMs are designed for high-performance networks and communications systems running at speeds of 200 megahertz and which require low latencies and fast random cycle times for operations such as wire-speed buffers, look-up tables and queues.
The PayloadPlus SDE 3.0 features OC-192c/10 Gigabit Ethernet (GbE) simulation support and enhanced debugging capabilities. It is designed to help customers quickly design, evaluate and debug PayloadPlus-based application programs and speed time-to-market. The new SDE, which is targeted to network system builders who develop or evaluate wire-speed packet/cell processing software, provides code compatibility from OC-12 through OC-192c/10 GbE speeds and beyond.
The new SDE speeds the development of Functional Programming Language (FPL) and Agere Scripting Language (ASL) scripts for Agere's PayloadPlus family of network processors. With its high-level FPL and ASL languages for OC-48c and 10-gigabit-per-second (Gbit/s) network processors, associated application programming interfaces (APIs) and XML-based hardware/software environment configuration, the SDE will enable faster development cycles, easier software maintenance and evolution and lower lifetime system costs.
Agere's FPL is a high-level language that offers dramatic code reduction, with each line roughly equivalent to 10 to 20 lines of C code. The FPL compiler is used in conjunction with Agere's Fast Pattern Processor (FPP) and/or NP10 network processor for reassembling and classifying incoming protocol data units (PDUs). Included in Agere's SDE is an FPL compiler with enhanced debugger, an Agere ASL compiler, PayloadPlus chip set simulators, a traffic generator, Agere API software, an enhanced graphical interface, and associated utilities. The XML-based hardware and software configuration environment allows customers to add and configure custom chips and logic along with the Agere Payload Plus network processing solution. The ASL compiler is coupled with Agere's Routing Switch Processor (RSP), Agere System Interface (ASI), and/or NP10/TM10 traffic manager devices, for policing, statistics, packet modification, and traffic management. The traffic generator utility produces simulated traffic files for the simulator. The Agere API provides low-level run-time access to the PayloadPlus chip set. Scripts and models developed on the SDE are compatible with all announced PayloadPlus chip sets and are expected to be compatible with follow-on generations of Agere's PayloadPlus network processor family. The graphical interface configures application parameters and runs the compilers, simulators and utilities.
The PayloadPlus SDE 3.0 supports the Windows NT, Red Hat, Linux, and Solaris environments. Available now, the PayloadPlus SDE 3.0 is part of a comprehensive development environment that covers both hardware and software components. This includes OC48c through OC-192c/10 GbE hardware development platforms (2.5 Gbit/s through 10 Gbit/s). Pricing is dependent upon final configuration.
About Fujitsu Microelectronics America:
Fujitsu Microelectronics America (FMA) is a supplier of semiconductors and electronics products. For more information, visit www.fma.fujitsu.com.
About Agere Systems:
Agere Systems is a provider of components for communications Applications, optical components and integrated circuits. For more information, visit www.agere.com.