MoSys adds RS-FEC, multi-link gearbox ICs to LineSpeed 100G PHY line

Sept. 24, 2015
Communications semiconductor developer MoSys (NASDAQ: MOSY) says it has extended its line of LineSpeed 100G PHYs with the MSH321 100-Gbps multi-link gearbox (MLG) and the MSH221 octal 100-Gbps retimer with Reed Solomon forward error correction (RS-FEC).

Communications semiconductor developer MoSys (NASDAQ: MOSY) says it has extended its line of LineSpeed 100G PHYs with the MSH321 100-Gbps multi-link gearbox (MLG) and the MSH221 octal 100-Gbps retimer with Reed Solomon forward error correction (RS-FEC).

The MSH321 MLG is designed to enable high-density, independent 10 Gigabit Ethernet and 40 Gigabit Ethernet interfaces to be multiplexed into a single 100 Gigabit Ethernet interface. It supports both OIF MLG-1.0 and MLG-2.0 standards and aggregates a combination of 10 Gigabit Etheret and 40 Gigabit Ethernet links into a single 100 Gigabit Ethernet (4x25G) link. Unlike a standard gearbox based on IEEE 802.3ba, the MLG does not require all 10 lanes to be bonded as 10x10G with zero ppm offset; it enables independent 10 Gigabit Ethernet or 40 Gigabit Ethernet lanes, separated by up to +/- 100 ppm, to be multiplexed into a single 100 Gigabit Ethernet stream.

The MLG device performs all alignment marker insertion and awareness, idle insertion and deletion, and data alignment required by the OIF MLG standards, MoSys says. The company sees a demand for the device as physical interfaces on switching and packet processing ICs move to 25G PHY interfaces, thus enabling systems to support higher port counts of legacy 10 Gigabit Ethernet and 40 Gigabit Ethernet interfaces.

The MSH221 retimer, with 802.3bj 100-Gbps RS-FEC, helps 4x25-Gbps interfaces to be compliant to the latest 100-Gbps IEEE standards and multi-source agreements (MSA), including SR4, CWDM4, PSM4, and others specified with FEC. It will supports up to four full duplex lanes (eight channels) with independent rates up to 28 Gbps for high data rate line card applications up to terabits per second. The multi-protocol SerDes device includes an option for the Clause 91 RS-FEC specified in 802.3bj for 4x25G NRZ interfaces.

When the RS-FEC is turned off, the MSH221 will function as a standard multi-rate and multi-protocol retimer capable of passing either encoded or non-encoded data. Each lane is independent and will support frequencies compatible with 10G, 25G, 40G and 100G Ethernet and OTN standards. With the 100G 802.3bj RS-FEC encode, decode, and correction functions enabled, the MSH221 will encode data in one direction and decode and correct data (if needed) in the other.

"We see the 100G network and data center infrastructure expanding, driven by the broad availability of the latest silicon and optical module technology," said Loring Wirbel, senior analyst with The Linley Group, via a MoSys press release. "Devices such as MoSys's latest LineSpeed PHYs -- which are on the forefront of supporting OIF MLG 1.0 and 2.0 and which support the latest 100G standards to enable higher 10, 40, and 100G port density; low-cost optical modules; and broad interoperability -- will be essential to that growth opportunity."

For more information on communications semiconductors and suppliers, visit the Lightwave Buyer's Guide.

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