Optical Tech

Xilinx intros Virtex-5 FPGA-based offerings for SPI-4.2 and SFI-4.1 interfaces

Dec. 4, 2007

DECEMBER 4, 2007 -- Verified across multiple FPGA platforms, the new offerings accelerate the design cycle of wired networking systems that require OC-192 (10-Gbit/sec), multiple OC-48 (2.5-Gbit/sec) or 10-Gigabit Ethernet (10-GbE) interfaces, resulting in much faster time-to-market than competing offerings, say Xilinx representatives.

DECEMBER 4, 2007 -- Programmable logic provider Xilinx Inc. (search for Xilinx) today announced a complete offering for the Optical Internetworking Forum (OIF) System Packet Interface (SPI) 4.2 and SerDes Framer Interface (SFI) 4.1 standards, the industry's highest performance channelized packet interfaces. Based on its Virtex-5 LXT FPGAs (search for FPGA), the offering features the ML550 hardware verification board, SPI-4.2 LogiCORE IP, and SFI-4.1 reference design.

Verified across multiple FPGA platforms, the new offerings accelerate the design cycle of wired networking systems that require OC-192 (10-Gbit/sec), multiple OC-48 (2.5-Gbit/sec) or 10-Gigabit Ethernet (10-GbE) interfaces, resulting in much faster time-to-market than competing offerings, say Xilinx representatives.

"High-speed standards such as SPI-4.2 and SFI-4.1 are used in demanding applications that require proven silicon, reliable and precise data capture, IP cores, and simple integration," explains Anil Telikepalli, senior manager of Platform Solutions Marketing at Xilinx. "Our field-tested and hardware-verified Virtex-5 FPGA solutions for SPI-4.2 and SFI-4.1 dramatically reduce design risk while providing the highest bandwidth," he contends.

The Xilinx ML550Iboard is ideal for development and evaluation of OIF and other networking interfaces, allowing designers to implement high-speed applications with extreme flexibility, says the company. Xilinx's ChipSync technology, available only in Virtex-5 FPGAs, provides accurate dynamic alignment of clock and data using 75 ps programmable delays, enabling improved timing and reliable operation under changing system conditions, note Xilinx representatives.

Xilinx says its SPI-4.2 LogiCORE IP, which is fully compliant with the OIF SPI-4.2 standard, interconnects physical layer ASSPs to link layer FPGA devices in a range of networking applications and multi-service DWDM and SONET/SDH-based transport systems. According to the company, the Xilinx SPI-4.2 IP core provides interoperability with industry-leading ASSPs and provides up to 20% higher data bandwidth due to optimized payload efficiencies as compared to competing FPGA offerings. The Xilinx SFI-4.1 reference design supports up to 710 Mbits/sec per channel with dynamic alignment to provide a robust offering for OC- 192 framer interfaces.

The SFI-4.1 reference design is immediately available free of charge. The SPI-4.2 LogiCORE IP is available for a free evaluation and can be purchased for an $18,000 site license fee. The Virtex-5 LXT FPGA ML550 board is available for $2,200.

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