NOVEMBER 21, 2006 -- RAD Data Communications will introduce TDM pseudowire gateway products that support all industry TDM pseudowire modes at ITU Telecom World 2006, to be held December 4-8 in Hong Kong.
RAD's new TDM pseudowire gateways are unique, the company says, because they will incorporate a high-performance ASIC chip, developed by RAD, that supports SAToP (Structure Agnostic TDM over Packet) and the two IETF informational RFCs: CESoPSN (Circuit Emulation Service over Packet Switched Network), and TDMoIP (TDM over IP). In addition, the new devices support HDLCoPSN, an IETF standard, optimizing bandwidth for HDLC-based services such as Frame Relay, X.25, and serial data traffic over packet-based networks.
"Pseudowire solutions are rapidly becoming a must-have element in carrier portfolios to ensure a complete multiservice offering over packet-based networks," states Ron Agam, senior product line manager at RAD Data Communications. "Carriers, on the other hand, want the widest possible range of choices in deciding which flavor of TDM pseudowire is best able to support their application.
"For this reason, multi-standard support is high on their checklist of product feature requirements. Embedding this functionality in hardware offers the advantage of low latency, low delay, low cost, and high-performance processing, avoiding operational downsides associated with software implementations," Agam concludes.
Since highly accurate TDM clock recovery is the paramount issue for TDM circuit emulation, RAD's third-generation ASIC also incorporates an advanced adaptive clock recovery mechanism, with accuracy of 16 parts per billion, conforming to G.823 traffic and synchronization specifications for jitter and wander as well as the new ITU-T G.8261 Recommendation, specifying synchronization over packet requirements.
"Delivering carrier-class TDM services requires sophisticated clock recovery technology in addition to pseudowire technology," adds Agam. "This processing is computationally intensive and there is a clear advantage to having the clock recovery algorithm wired into the silicon."
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