Improving measurement resolution for Fibre Channel devices

Aug. 1, 1997

Improving measurement resolution for Fibre Channel devices

A combination of parallel and serial bit-error-rate testers is necessary to ensure that faults can be isolated effectively.

Ed Vitiello Tektronix Inc.

Mike Anderson Maxim Integrated Products

High-speed serial technologies such as Fibre Channel are becoming more common as they gain market acceptance. Developing these technologies requires a great deal of testing, reliable instruments with high resolution, and carefully designed fixture interfaces. One key challenge facing Fibre Channel designers is measurement resolution. When failures occur, how can they be isolated to a serializer or deserializer?

Parallel bit-error-rate testers (berts) can separate these functional blocks and provide enhanced measurement resolution. When testing Fibre Channel transmitter or serializer functions, the parallel bert can be used as a pattern generator for serial measurements that include rise/fall times, output levels, and jitter. When testing Fibre Channel receiver or deserializer functions, the tester can be used to make measurements such as amplitude sensitivity and jitter tolerance. Figure 1 illustrates some of the different test applications central to all transceiver measurements.

Using a parallel bert can reduce test interface complexity, minimize equipment needs, simplify conformance testing, and most important, allow the transmitter and receiver to be isolated for each measurement. This is a vast improvement compared to using only serial test equipment, which requires loopback of the parallel Fibre Channel data bus.

Fibre Channel basics

Fibre Channel, as defined by ansi X3.230-1994, "Fibre Channel--Physical and Signaling Interface (fc-pc), Rev. 4.3," is a high-speed serial technology that can use either copper or optical media. "Fiber" is a general term used to cover all physical media types supported by Fibre Channel, including optical fiber, twisted pair, and coaxial cable. At 1.0625 Gbits/sec, a copper Fibre Channel link can be usable up to 30 m, and an optical link can have a length of approximately several kilometers.

Fibre Channel serial data is 8B/10B-encoded. That is, 8-bit parallel data is encoded to 10-bit data to produce a bit stream suitable for high-speed serial transmission. No more than four consecutive ones or zeros are permitted in the transmission, except in the case of a special character, where there are five consecutive ones or zeros. The maximum run length of the code is limited to assist the clock-recovery phase-locked loop (pll) in maintaining phase lock on the incoming data. In addition, the data is encoded such that a DC balance is maintained.

Fibre Channel`s encoding reduces transmission errors by ensuring that enough transitions are present on the serial bit stream to permit clock recovery. It also facilitates error detection and assists in word alignment at the receiver. This process is patented by ibm, which has agreed to a royalty-free, one-time documentation fee for use of its patent.

Fibre Channel transceivers are currently being designed to the 10-bit specification proposed by the American National Standards Institute--ansi tr/x3.18-199x, "Fibre Channel--10-bit Interface, Draft proposed X3 Technical Report." On the transmit parallel bus, only 11 signals are defined (see Fig. 2). The refclk signal latches the 10 bits of data--TX[9:0]--into the transmitter.

The receiver uses two 53.125-MHz clocks to clock out the 10-bit parallel bus. In addition, there is the -lckref input that selects whether the clock-recovery pll locks to the local reference or to the incoming serial data. The en_cdet signal is used to align the byte to the comma character, and com_det indicates when lock occurs by going high. The ewrap input internally wraps the serial data from the transmitter directly to the receiver.

berts are the basic tool for testing the quality of transmission systems and circuit elements. The job of the bert is to feed test patterns bit-by-bit through the transmission path or device under test (dut) and measure the error rate. Bit-error rates (bers) represent a simple calculation of the number of bit errors over the total number of bits sent. Typical acceptable error rates might be one in one billion bits or lower, but rates will vary by application. Unlike serial berts that allow for only one clock and data signal, parallel berts provide multichannel stimulus and analysis.

Verifying Fibre Channel compliance

Numerous measurements are needed to verify Fibre Channel compliance. When dealing with the 10-bit interface, these include setup and hold timing, jitter generation, jitter tolerance, and ber. Combinations of serial and parallel test equipment provide the best measurement resolution.

ber is measured on serializer and deserializer functions using combinations of parallel/serial bert equipment or a parallel bert with serial Fibre Channel data looped back. Because Fibre Channel is used primarily as a data-communications channel, ber is a central issue. The most likely place for a bit error to occur is in the serial receiver. This is where the data is sampled by a recovered clock.

Intersymbol interference (isi) is a primary cause for bit errors. With copper media, isi increases with the length of the media. Fibre Channel specifies that a link may have a ber no greater than 10-12. However, many transceiver vendors test their parts to a tighter specification.

At 1 Gbit/sec, it takes approximately 17 minutes to communicate 10-12 bits. Estimating the actual error rate requires some assumptions about the randomness of errors [see "Measuring Error Rate Quickly and Accurately," Dan Wolaver, Tektronix, Microwave Logic Group, December 1993]. It requires 1.2 days of testing to measure a ber of 10-12 to a 90% confidence level. However, to reduce test times, stress can be added to the system.

Transmit setup and hold measurements can be made using a parallel bert as the stimulus source and a serial bert as the measurement device. To qualify these timing definitions, the phase of the refclk input can be varied with respect to the parallel data supplied by a bert pattern generator. To verify that each channel complies with setup and hold times, each bit on the 10-bit bus should be toggled on each clock cycle. Testing involves advancing or delaying the clock edge in 100-psec increments until errors occur.

Receive setup and hold measurements can be made using either the parallel or serial bert as the stimulus source and the parallel bert as the measurement device. The bert stimulus source drives a known pattern that causes each receiver line to toggle.

Measuring receive setup and hold times requires a clock-doubling synthesizer (see Fig. 3). This is because the parallel bert requires a single 106.25-MHz receive clock to latch the 10-bit parallel data, whereas 10-bit transceivers employ two 53.125-MHz clocks latching the data onto the rising edge of each clock. Care must be taken when interfacing these signals, because even though this is the slow side of the transceiver, it is still operating at 106.25 Mbits/sec.

The synthesizer will probably present a different load to the parallel output signals than does the bert. Such unmatched loads can cause skews and mismatched rise and fall times. To remedy this, the clocks and data lines should be buffered before driving the synthesizer and bert error generator. Select a buffer chip that has enough current to drive the synthesizer and place the synthesizer close to the buffer chip.

Either rbc clock can be used to drive the clock doubler, as long as any skew between the rbc clocks is noted in the measurement. To make this measurement, use the bert error detector to delay or advance the doubled rbc clock in 100-psec increments with respect to the parallel data inputs. Record the setup and hold times that cause the first bit errors to occur.

A jitter-generation measurement can be made by using a parallel bert as the stimulus source and a jitter measurement instrument or oscilloscope as the measurement device. Jitter generation is simply the amount of jitter measured at the Fibre Channel transmitter serial output. Because jitter will be related to the data pattern, a special test pattern, described below, is required.

Jitter tolerance testing measures the performance of the Fibre Channel receiver in the presence of jitter. To accomplish the measurement, jitter is induced at distinct amplitude and frequencies onto a serial bit stream and is then input into the receiver. A parallel bert error detector measures the ber of the recovered data.

For many compliance tests, you can use short patterns of encoded data as the test stimulus to verify system operation and de-bug test setups. One such pattern is called the Idle Primitive, which is a four-character ordered set that is continuously sent when no data is present or serves as a filler between frame transmissions.

An Idle Primitive consists of the special comma character "K28.5" followed by "D21.4, D21.5, and D21.5." The K28.5 character is the first character of this ordered set. Deserializers use it along with the comma detect function to align the 10-bit boundaries. When its en_cdet input is enabled, the deserializer searches for K28.5 characters to perform byte alignment. The D21.5 character, which provides transitions on every bit, appears twice in the Idle Primitive to enable the clock-recovery pll to maintain lock.

For the setup and hold tests, you can create a short test pattern that will toggle each data line by simply repeating the comma character (K28.5) with alternating disparity.

The ansi Fibre Channel Methodology for Jitter Specification group (mjs) has prepared a technical document recommending a pattern for measuring jitter for Fibre Channel receivers ("Fibre Channel--Fibre Channel Methodologies for Jitter Specification," Draft proposed X3 Technical Report). It proposes a pattern that can be used to measure both jitter generation and jitter tolerance. This jitter generation pattern consists of six Idle Primitives, a Start of Frame (sof), a 12-byte pattern repeated 16 times, an error-correction code (crc), and an End of Frame (eof).

Wiring

It is impossible to predict the best types of fixture or wiring methods to use for various Fibre Channel measurements. In almost every case, the best rule of thumb is to use the shortest possible wire length between the dut and test system.

To simplify test connections, consider designing a special-purpose test interface fixture. Using such a custom printed circuit board, you can route critical clock and data signals from your dut to appropriate buffer devices, terminations, and interface connectors. A properly designed interface will provide reliable connections, improved signal integrity, and easy instrument access.

Important considerations for all high-speed fixtures include matched impedance traces for critical high-speed clock and data signals; provisions for adding termination networks at dut inputs; and provisions for connecting low-current device outputs (ttl/cmos) to buffers or line drivers. These will be needed to drive high-speed output signals over coaxial cables. In addition, sma or other high-frequency connectors are required to interface to your high-speed test equipment. Also include a few pull-up and pull-down resistors on your test fixture. Wire these to a few convenient test points. They are useful for setting up static conditions during testing.

Isolating Fibre Channel measurements to the serializer or deserializer using parallel berts gives engineers the ability to focus on the critical functions. This is a vast improvement over applications using only serial test equipment, because such test methods require loopback of the parallel Fibre Channel data bus. With this improved measurement resolution, engineers can more easily identify sources of compliance, performance, and operational problems. u

Ed Vitiello is an application engineer at Tektronix Inc.`s Chelmsford, MA, field office. Mike Anderson, formerly of Symbios Logic in Fort Collins, CO, is an analog design engineer at Maxim Integrated Products, Colorado Springs, CO.

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