APRIL 16, 2007 -- Lattice Semiconductor Corp. has announced the availability of its PURESPEED I/O Burst Mode Receiver (BMR) FPGA Reference Design for GPON. This reference design uses Lattice's Adaptive Input Logic (AIL) block found on its LatticeSC FPGAs and LatticeSCM FPGAs (collectively, the LatticeSC/M family) to rapidly establish stable clock to data timing relationships within the fast lock times specified in the GPON ITU-T G.984.1 specification, which requires the optical line termination (OLT) to lock to incoming data within 50 bit times.
"The ability of our PURESPEED I/O System to function as an OLT burst-mode receiver using the AIL block is one of the genuine differentiators of the LatticeSC/M family," said Stan Kopec, Lattice corporate vice president of marketing. "Terminating upstream GPON traffic using a mere 150 mW of power is a huge advantage to customers when compared to 400 mW for the nearest programmable solution and 1 W for standard products. With this solution, our customers are able to terminate multiple GPON channels on a single FPGA in a remarkably compact 256 BGA package."
The OLT in a GPON receives data from the optical network termination (ONT) in bursts, and so needs to quickly lock on to data as it is sent. Traditional Ethernet and SONET clock and data recovery (CDRs) devices have inherently long lock times and latencies, making them difficult or impossible to use in the upstream direction. The Lattice BMR chip leverages the fast locking, low latency AIL circuitry in the PURESPEED I/O to perform the data recovery, making it the smallest footprint and lowest power FPGA-based BMR solution available today, the company asserts.
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