September 24, 2002 - Agilent Technologies introduced the Agilent HDMP-3002 Gigabit Ethernet over SONET (EoS) mapper chip. The single-chip solution is the industry's first EoS mapper chip to integrate SerDes, clock data recovery, and OC-3 to OC-48 framers, three features required to efficiently format data for SONET/SDH networks. The new chip is expected to save network equipment manufacturers design and test time, board space, power consumption and system costs.
The HDMP-3002 is the second member of Agilent's multi-protocol IC (MPIC) family. MPICs take protocol independent traffic and map it into SONET/SDH, providing a solution for loading enterprise data traffic onto a SONET/SDH metro infrastructure.
The chip provides full-duplex mapping of Fast Ethernet and Gigabit Ethernet frames encapsulated into STS-48/12/3 SONET/SDH payload using the generic framing procedures, frame delineated high-level data link control (per RFC 1662/2615), or the link access procedure-SDH protocol. The device can connect up to four Gigabit Ethernet feeds into one STS-48/STM-16 (2.488-Gbit/sec), four STS-12/STM-4 (622-Mbit/sec), or four STS-3/STM-1 (155-Mbit/sec) channels. Its virtual concatenation feature allows service providers to dial up "bandwidth on demand" for customers, allocating bandwidth data streams as small as STS-1 (51.8 Mbit/sec) granularity. Virtual concatenation eliminates the bandwidth inefficiency and long provisioning delays of legacy SONET/SDH transport networks.
The HDMP-3002 is part of Agilent's METRAK family of fiber-optic transceivers and ICs aimed at metropolitan network applications. It is designed for use in multi-service provisioning platforms, edge routers and line cards for SONET add/drop multiplexers within the LAN and metro-access(edge) network. The edge network is where the carrier-owned WAN meets the corporate-owned LAN. The EoS mapper provides access to SONET/SDH overhead collection, allowing carriers to manage their networks. It also offers the performance monitoring carriers require without the need for costly layer-3 processing.
The EoS mapper is a highly integrated, layer-2 solution that is implemented in a low-power 0.18 micron CMOS process with a 1.8 V core, 2.5 V and 3.3 V I/Os. The device is supplied in a 664-pin ceramic ball grid array package and supports the OC-48/STM-16 standard. More information is available at www.agilent.com.