Low-jitter, non-PLL clock, switchover 2:1 multiplexers prevent runt pulses

March 28, 2005
March 28, 2005 San Jose, CA -- Micrel, a developer of analog, high-bandwidth, and Ethernet IC platforms, has launched its SY8984x MUX series of high-performance, ultra-low jitter LVDS, CML, and LVPECL clock multiplexer ICs. The chips feature the company's patent-pending runt-pulse elimination (RPE) and Fail Safe Input (FSI) circuitry.

March 28, 2005 San Jose, CA -- Micrel, a developer of analog, high-bandwidth, and Ethernet IC platforms, has launched its SY8984x MUX series of high-performance, ultra-low jitter LVDS, CML, and LVPECL clock multiplexer ICs. The chips feature the company's patent-pending runt-pulse elimination (RPE) and Fail Safe Input (FSI) circuitry.

"The SY8984x series addresses a number of technical challenges for designers," explains Thomas S. Wong, vice president of high bandwidth products at Micrel. "RPE technology eliminates the short cycles during switching, while the FSI technology protects unwanted oscillations due to various faults at the inputs."

According to the company, its SY89840U-SY89843U and SY89837/8U devices offer the industry's first non-PLL clock switchover (primary-to-secondary) circuit that guarantees no runt pulses (short cycles) when the inputs are switched. Optimized for precision clock switching architectures in enterprise server and non-SONET based networking systems, the company says these multiplexers provide an ultra-low jitter, low cost, precision alternative to PLL switching designs. Notably, one of the platform's features is an input stage that prevents unwanted oscillations and maintains output stability when an input signal's differential signal collapses or disappears.

"Micrel's proprietary design for internal termination is also incorporated to eliminate stubs," continues Wong. "In addition, our continued focus on MLF packaging, featuring low inductance and capacitance, makes the SY8984x series ideal for today's high-speed, economical designs."

According to the company, the SY89840U-SY89843U MUX series and SY89837/8 LVDS integrated fanout buffers minimize jitter and simplify designs using integrated internal termination. The company says this unique, patented input is designed to interface to any differential signal, AC- or DC- coupled, without any external components in the signal path. According to the company, another distinctive feature designed to minimize jitter is a superior MUX input crosstalk isolation design that reduces crosstalk by up to 70 percent.

The company says its RPE/FSI multiplexers feature an AC performance that guarantees clock frequency throughput from 1kHz to 1.5GHz, and rise and fall times of 250ps for LVDS and LVPECL outputs, and 150ps for CML outputs. CML output options include internal source termination to reduce round-trip reflections and maintain low-jitter performance. Jitter performance is guaranteed to be less than 10psp-p, and within device, output-to-output skew is guaranteed to be less than 25ps. The product family guarantees operation over the full industrial temperature range (-40C to +85C) and supply voltage operation from 2.5V or 3.3V.

The SY89837/8U LVDS fanout buffers, with RPE/FSI MUX inputs, are available in volume quantities. SY89842U and SY89843U RPE/FSI multiplexers will, according to the company, be available in volume quantities by the end of April 2005. Evaluation boards for all devices are also available. Pricing for ICs starts at $2.55, for 1K quantities.

Sponsored Recommendations

Linear Pluggable Optics – The low-power optical interconnects for AI and Hyperscaled data centers.

Dec. 23, 2024
This LightWave webinar discussion will review the important technical differentiators found in this emerging interconnect field and how the electro/optic interoperability and ...

State of the Market: AI is Driving New Thinking in the Optical Industry

Dec. 5, 2024
The year 2024 marked an inflection point for AI. In August, OpenAI’s ChatGPT reached 200 million weekly active users. Meanwhile, McKinsey reported that 72% of ...

Getting ready for 800G-1.6T DWDM optical transport

Dec. 16, 2024
Join as Koby Reshef, CEO of Packetlight Networks addresses challenges with three key technological advancements set to shape the industry in 2025.

The Road to 800G/1.6T in the Data Center

Oct. 31, 2024
Join us as we discuss the opportunities, challenges, and technologies enabling the realization and rapid adoption of cost-effective 800G and 1.6T+ optical connectivity solutions...