Anritsu MUX MP1861A/DEMUX MP1862A

The 56G/64G MUX MP1861A and 56G/64G DEMUX MP1862A help engineers ensure the signal integrity of PHY devices such as SERDES used such high-speed interfaces as 400 Gigabit Ethernet and CEI-56G. Linking the MUX MP1861A and DEMUX MP1862A with the MP1800A BERT Signal Quality Analyzer with its 32G pulse pattern generator/error detector and jitter modulation source supports generation of NRZ data signals at up to 64 Gbps, BER measurements, and jitter tolerance measurements. New standards such as CEI-56G are also supported by jitter tolerance measurements of jitter components such as Dual Tone SJ, RJ, BUJ, SSC, and Half Period Jitter, as well as bathtub jitter measurements. The addition of the MUX MP1861A and DEMUX MP1862A helps to establish the ideal total solution for signal integrity evaluation the emerging, high-speed designs.