Agere Systems launches FlexPHY chip

Dec. 16, 2002
16 December 2002 -- Agere Systems has introduced the FlexPHY integrated circuit, a single-chip physical layer (PHY) transceiver that reduces space and power by more than 50 percent over existing solutions.

16 December 2002 -- Agere Systems has introduced the FlexPHY integrated circuit, a single-chip physical layer (PHY) transceiver that reduces space and power by more than 50 percent over existing solutions. and enables the highest transmission signal quality for today's multi-service metropolitan edge to core networks.

The FlexPHY device, says Agere, breaks all performance records of previous Agere PHY chips, offering "the industry's best performance, jitter margins, power consumption and integration for system vendors targeting 10Gbit SONET/SDH, Ethernet (10GE) and Fibre Channel (10GFC) networks. Samples of the FlexPHY chip should be available in Q1 2003, with volume production expected by Q2.

The company believes that the market for 10-gigabit PHYs is one positive spot of growth in the capex-constrained telecom market. And Sean Lavey, an analyst with IDC agrees: "Sales in this product segment are expected to grow from USD276min in 2003 to USD780m in 2006."

A PHY transceiver chip transmits and receives data between the physical (optical fibre) and information processing layers. On a network line card, Agere's FlexPHY chip resides at the boundary between the protocol framer and the optics, providing the bridge for improved, multi-rate optical performance with multi-protocol support for the framer.

Agere recently introduced its MARS (Multi-Application and Rate Solutions) family of chips, an integrated range of framers for multi-service metropolitan and access networks.

The FlexPHY chip offers more than double the density of competitive offerings and uses industry-leading multi-rate, multi-protocol, signal integrity technology. The FlexPHY IC can be used in more communication network applications than comparable chips, from ATM and Ethernet switches and routers connecting data centres and IT infrastructure, to multiplexers and dense wave division multiplexed (DWDM) optical backbone transport systems.

The chip's jitter generation is as low as 30 milli-unit interval peak-to-peak ? which Agere says is the the industry's best performance in this area. Most competitive single-chip CMOS devices have jitter generation of greater than 50 mUI, pk-pk. A typical network system jitter generation budget is 100 mUI pk-pk.

The low generated jitter allows for additional flexibility in system design and makes the FlexPHY chip suitable for all optical networking applications from very short reach (VSR) to ultra-long reach (ULR), including DWDM.

To reduce board usage, increase performance, flexibility and functionality, the FlexPHY chip integrates a clock multiplier unit (CMU), 16:1 multiplexer and 1:16 demultiplexer functions into a single device. It incorporates a highly sensitive (less than 10 mV) limiting amplifier with programmable amplitude threshold adjustment, as well as clock data recovery (CDR) function with programmable phase sampling point adjustment.

Furthermore, the FlexPHY IC offers a low power consumption. It has a total average power consumption of 1.0 W versus most competitive solutions' 1.4 W to 2.0 W of power consumption. The FlexPHY chip's low power specification is key to developing high-density board designs for space-constrained equipment, improved performance and reliability

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