Infineon demonstrates first CMOS 40Gbit/s mux/demux

Nov. 30, 2002
29 November 2002 -- Infineon Technologies has demonstrated a multiplexer/demultiplexer chip-set with a record transmission rate of 40Gbit/s for CMOS.

29 November 2002 -- Researchers at Munich-based Infineon Technologies have demonstrated a multiplexer/demultiplexer chip-set using 0.13 micron complementary metal-oxide semiconductor (CMOS) technology that achieves a transmission rate of 40Gbit/s.

This breaks its own previous record of 25Gbit/s for high-frequency communication ICs using CMOS process technology. This was done by using optimised circuit techniques and by using the CMOS process with maximum efficiency, says Infineon.

The goal of the research was to achieve 40Gbit/s high-frequency circuits using proven, low-cost CMOS technology, a target previously only possible using silicon-germanium (SiGe) bipolar transistor technology or more complicated and expensive gallium arsenide (GaAs) or indium phosphide (InP) process techniques.

The major benefit of CMOS is high integration density, which allows the integration of complex logic together with the new high-speed circuits. Multifunctional multiplexer/demultiplexer chip-sets have until now been realised using separate SiGe RF components and CMOS logic chips (currently marketed by Infineon).

Monolithic integration is the next stage of development. This has technical and financial advantages because it reduces the total power consumption of an integrated solution, increases manufacturing output and lowers production costs.

The mux/demux chipset was implemented using current mode logic and differential 50 Ohm I/O. A modified form of this circuit technique, which is widely used in SiGe bipolar technology, has now also been successfully used in CMOS. Infineon says that the high data rate of more than 40Gbit/s originates from careful circuit optimisation: pre-latch configuration, transistor size, operating current per stage, gain peaking due inductive loads and a new type of output signal transmission optimisation from chip to the outside.

The data multiplexer (2:1) achieved a maximum transmission rate of 43Gbit/s in initial tests. It used a 1.5V power supply and has power consumption of just 66mA. The data demultiplexer (1:2) also used 1.5V and has power consumption of 72mA. The maximum data speed for the demultiplexer was measured at 40Gbit/s.

www.infineon.com

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